Oracle Server - SPARC M10 - Architecture

In SPARC M10 systems, processors, system interconnects, and the memory and I/O subsystems work in concert to create a scalable, high-performance platform ready to address a wide range of workloads, from consolidation of general purpose enterprise computing to the fastest, largest, and most secure database processing.
The design of the SPARC M10 systems focuses on high reliability, and places emphasis on maximizing the merits of memory locality in a ccNUMA architecture to deliver outstanding performance. The characteristics and capabilities of every subsystem within the SPARC M10 systems work toward this goal. A high-bandwidth system bus, powerful SPARC64TM X processors, dense memory support, and fast PCI Express combine within the SPARC M10 systems to deliver the highest levels of uptime and throughput, as well as dependable scaling for enterprise applications.

• DDR3 DIMMs

• PCI express generation3

• High speed interconnection between CPUs (14.5Gbps)

• SPARC64 X Processor

• Cache Coherent Non-Uniform Memory Architecture (ccNUMA)

• System on Chip (SOC) to achieve shorter memory latency and wider bandwidth

• Liquid Loop Cooling (LLC) system to achieve high density packaging

Usefull Link

Oacle-fujitsu-m10-server-features-and-capabilities

Oracle Sparc m10 series-servers_introduction_and_overview

Oracle Sparc m10 series-servers_installation

Oracle Sparc m10 series-servers _architecture

1. High-Speed Interconnect

The system interconnect underpins the highest levels of performance, scalability and reliability for the SPARC M10 systems. Multiple system controllers and crossbar units within the SPARC M10 systems provide point-to-point connections between CPU, memory, and I/O subsystems. Offering more than one bus route between components enhances performance and allows system operation to continue in the event of a fault. The system interconnect used in the SPARC M10 systems delivers as much as 6553 GB/second of peak bandwidth, offering nine times more system throughput than Fujitsu’s previous generation of high-end servers

2. Software on Chip

• Database Accelerator Engine Decimal Arithmetic Logical Units embedded in processor

• Supports decimal floating-point processing based on IEEE Standard(IEEE754) and Oracle Number

• HPC-ACE SIMD(Single Instruction Multiple Data)

• High speed arithmetic processing by four elements in a single instruction (Application of supercomputer technology)

• Encryption/Decryption Engine

• Supports cryptographic algorism: AES, DES, 3DES, RSA, and SHA

3. Liquid Loop Cooling

4. XSCF

• Each building block and XB-BOX has a XSCF, that is not redundant in a single building block.

• In a M10-4S system with 2 or more building blocks, XSCFs in the system form redundancy. System consists of one Master, one Stand-by and remaining Slave XSCFs.

• Interconnection between Master, Stand-by and Slave XSCFs is called SSCP (SP to SP Communication Protocol)

• Same revision of XCP is running on all the XSCFs, except intermediate status during firmware update

• VBSC/LDC (communication between XSCF and domain, or domains)

• No new protocol added on the top of VBSC/LDC. This is almost same as T-Series servers

• Some enhancements for SPARC M10 are done by adding commands or parameters on top of BSC/LDC. Enhanced items are as follows:

• PCIe Conf. notification

• Log notification to inform license violation of CPU core activation

• Reset/panic request to guest domain

• SSCP (communication between XSCFs)

• Protocol is usual TCP/IP, and is used to transfer all the information to be transferred between XSCFs

• Default SSCP address is used when XSCF starts. Administrator can change address to different one by setsscp command

5.  Physical Partition Console

Partition basic commands:
XSCF> setpcl -p 0 -a 0=00-0 1=01-0 2=02-0 3=03-0

XSCF> addboard –c assign –p 0 00-0 01-0 02-0 03-0

XSCF> poweron -p 0 -y
PPAR-IDs to power on:00
Continue? [y|n]:y
00:Powering on
*Note*
This command only issues the instruction to power-on.
The result of the instruction can be checked by the "showlogs power".

XSCF> poweron –a -y
PPAR-IDs to power on:00,01,02,03
Continue? [y|n]:y
00:Powering on
01:Powering on
02:Powering on
03:Powering on
*Note*
This command only issues the instruction to power-on.
The result of the instruction can be checked by the "showlogs power".

XSCF> console -p 0 -y
Console contents may be logged.
Connect to PPAR-ID 0?[y|n] :y
"#" and "." (period)

Useful Docs:
White Paper - SPARC M10 Server Architecture